Semiconductor Integrated Circuits Layout-DesigN

India’s legal framework for protecting semiconductor layout designs is governed by the Semiconductor Integrated Circuits Layout-Design Act, 2000. This legislation provides exclusive rights to creators of original and distinctive layout designs used in semiconductor integrated circuits.

Key highlights include:

· Definition: A layout design refers to the arrangement of transistors and circuitry elements, including lead wires, expressed in any form within a semiconductor integrated circuit.

· Eligibility for Registration: 

o The design must be original, distinctive, and capable of distinguishing from other designs.

o It must not have been commercially exploited in India or any convention country prior to filing.

· Who Can Apply: Indian nationals or nationals of reciprocating countries with a principal place of business or service in India may apply.

· Application Process: 

o Submit Form LD-1 with a ₹5,000 fee via Demand Draft.

o Include three sets of drawings or photographs of the mask layout, preferably in GDS-II format with PDK details.

o All documents must be submitted in triplicate in physical form.

· Validity: Protection lasts for 10 years from the date of filing or first commercial exploitation—whichever is earlier.

· Registration Cycle: 

o Filing, examination, acceptance/refusal/modification

o Advertisement within 14 days of acceptance

o Opposition period of 3 months

o Counter-statement and hearing, if opposed

o Final decision by Registrar, with appeal rights to the Appellate Board or Civil Court

This Act ensures that creators of semiconductor layouts receive legal protection for their intellectual efforts, fostering innovation in India’s electronics and chip design ecosystem.